Architecting Cpi Component Performance Counters

......A key application of user-visible hardware performance counters is to give the software developer clear, accurate, and useful hardware-related performance information. This information provides guidance on software changes that can improve performance. An intuitively appealing way to represent the major performance components is to quantify their contributions to the average cycles per instruction (CPI). However, for out-of-order superscalar processors, conventional performance counters don’t provide the type of information from which software developers can determine accurate CPI components. One reason is that hardware designers have historically constructed performance counters in a bottom-up fashion by focusing on individual events that affect performance, such as cache misses, without considering how to combine individual counts into a comprehensive picture of CPI components. In contrast, by viewing performance in a top-down manner with accurate CPI measures as the goal, designers can define a set of performance counters that provide basic data from which software developers can build an accurate overall CPI picture. We have developed such a top-down approach, beginning with a superscalar processor performance model called interval analysis. Interval analysis gives an in-depth understanding of relationships among miss events and related performance penalties. We use insights from the performance model to design a novel hardware performance counter architecture for computing CPI components that are accurate to within a few percent of CPI components computed by detailed simulations. This approach is Stijn Eyerman Lieven Eeckhout